A 1-GB SDRAM WITH GROUND-LEVEL PRECHARGED BIT-LINE AND NONBOOSTED 2.1-V WORD LINE

This paper describes the key technologies used in a I-Gb synchronous D RAM. This DRAM was developed according to a new cell-operating concept in which a ground-level (V-ss) precharged bit line with a negative wo rd-line reset scheme enables a nonboosted 2.1-V word-line architecture . Total power consumption is less than that of the conventional half-V -cc precharged bit-line scheme. We also propose a vernier-type, high-a ccuracy delay-locked-loop circuit realizing +/-20-ps quantization erro rs for clock recovery and skew elimination.