500-MB S NONPRECHARGED DATA BUS FOR HIGH-SPEED DRAMS/

A nonprecharged data-bus scheme to enhance the intrinsic read data rat e of DRAM cores is proposed, Eliminating the precharge cycle of the DR AM data bus can reduce the unit bit time. A differential partial respo nse detection data-bus amplifier is also employed to detect signals on the nonprecharged data bus that are degraded by large intersymbol int erference, To enhance the read operation further, column selections ar e overlapped by interleaved column decoders. To increase the operating margin of the nonprecharged data-bus read, a skew-controlled column-s election pulse generator was developed. An isolated sense-amplifier sc heme increases the write data rate of the DRAM core. To verify these s chemes, a 4-Mb DRAM was fabricated via 0.24-mu m DRAM technology. Thes e schemes realized a 500-Mb/s per data-bus read operation and a 400-Mb /s per data-bus write operation without an area penalty.