PROCESSOR-BASED BUILT-IN SELF-TEST FOR EMBEDDED DRAM

A built-in self-test engine and test methodology have been del eloped for testing a family of high-bandwidth, high-density DRAM micros. The DRAM macros [1] range in size from 256 x 16 x 128 to 2 K x: 16 x 256 ( Word x Bit x Data) and are targeted for embedded applications in appli cation-specific integrated circuit designs. The processor-based test e ngine, with two separate instruction storage memories, combines with f lexible address, data, and clock generators to provide DRAM highperfor mance ac testing using a minimum of dedicated test pins. Test results are compressed through on-macro, two-dimensional, redundancy allocatio n logic to provide direct programming information for the fuser via a serial scan port. The design is architected for reuse on future DRAM-g eneration subarrays and can be adapted to any number of address or dat a-pin configurations.