A 60-MW MPEG4 VIDEO CODEC USING CLUSTERED VOLTAGE SCALING WITH VARIABLE SUPPLY-VOLTAGE SCHEME

A 60-mW MPEG4 video codec has been developed for mobile multimedia app lications. This codec supports both the H.263 ITU-T recommendation and the simple profile of MPEG4 committee draft version 1 released in Nov ember 1997, It is composed of a 16-bit reduced instruction set compute r processor and several dedicated hardware engines so as to satisfy bo th power efficiency and programmability, It performs 10 frames/s of en coding and decoding with quarter-common intermediate format at 30 MHz. Several innovative low-power techniques were employed in both archite ctural and circuit levels, and the final power dissipation is 60 mW at 30 MHz, which is only 30% of the power dissipation for a conventional CMOS design. The chip was fabricated in a 0.3-mu m CMOS with double-w ell and triple-metal technology. It contains 3 million transistors, in cluding a 52-kB on-chip SRAM. Internal supply voltages of 2.5 and 1.75 V are generated by on-chip de-de converters from 3.3-V external suppl y voltage.