AN 800-MOPS, 110-MW, 1.5-V, PARALLEL DSP FOR MOBILE MULTIMEDIA PROCESSING

This paper presents a newly developed parallel digital signal processo r (DSP) for mobile multimedia processing. The DSP achieves 800 MOPS at 110 mW (1.5 V) through its task-parallel processing on four DSP cores . The parallel architecture, including data sharing and synchronizatio n mechanisms, is carefully designed to be hardware and power efficient for portable multimedia applications. By using the parallel processin g architecture, clock gating, and other low-power methods, about 85% p ower reduction is achieved. The 9.2-mm-square die contains 5.2-M trans istors with 0.25-mu m CMOS process.