A 240-MBPS, 1-W CMOS EPRML READ-CHANNEL LSI CHIP USING AN INTERLEAVEDSUBRANGING PIPELINE A D CONVERTER/

A 3.3-V, 1-W, 240-Mbps extended-partial-response maximum-likelihood re ad/write-channel large-scale-integration chip for hard disk drives has been developed. Power consumption of 1 W was achieved by using a 3.3- V power supply, a 0.4-mu m CMOS process, and a 3.3-V CMOS analog circu it design. Our approach to achieving a high transfer rate of 240 Mbps was to develop an interleaved subranging pipeline lookahead analog/dig ital (A/D) converter architecture, The power consumption of this A/D c onverter is 200 mW at 255 MHz, The read-mode channel path combines an acquisition-mode analog phase-locked loop (PLL) and a tracking-mode pr ecision digital PLL, enabling the use of a long-latency pipeline AID c onverter in the digital PLL, Consequently, a bit error rate of 10*(-9 ) at a signal-to-noise ratio of 24.5 dB has been achieved.