SCALABLE PD SOI CMOS WITH FLOATING BODIES

An insightful analysis of the Boating-body (FB) effect on off-state cu rrent (I-off) in PD/SOI MOSFET's is done based on simulations calibrat ed to a published scaled SOI CMOS technology [1], In contrast to the c onclusion drawn in [1], the simulations reveal that proven, easily int egrated processes for enhancing carrier recombination in the source/dr ain junction region, in conjunction with normal elevated chip temperat ure of operation, can effectively suppress the FB-induced increase of I-off, thus enabling exploitation of the unique benefits of scaled PD/ SOI CMOS circuits.