MOS-TRANSISTORS WITH STACKED SIO2-TA2O5-SIO2 GATE DIELECTRICS FOR GIGA-SCALE INTEGRATION OF CMOS TECHNOLOGIES

Advances in lithography and thinner SiO2 gate oxides have enabled the scaling of MOS technologies to sub-0.25-mu m feature size. High dielec tric constant materials, such as Ta2O5, have been suggested as a subst itute for SiO2 as the gate material beyond t(ox) approximate to 25 Ang strom. However, the Si-Ta2O5 material system suffers from unacceptable levels of bulk fixed charge, high density of interface trap states, a nd low silicon interface carrier mobility. In this paper we present a solution to these issues through a novel synthesis of a thermally grow n SiO2 (10 Angstrom)-Ta2O5 (MOCVD-50 Angstrom)- SiO2 (LPCVD-5 Angstrom ) stacked dielectric, Transistors fabricated using this stacked gate d ielectric exhibit excellent subthreshold behavior, saturation characte ristics, and drive currents.