A SIMPLE AND EFFICIENT SELF-LIMITING ERASE SCHEME FOR HIGH-PERFORMANCE SPLIT-GATE FLASH MEMORY CELLS

This paper presents a fast self-limiting erase scheme for split-gate f lash EEPROM's. In this technique the conventional erasing is rapidly f ollowed by an efficient soft programming to correct for over-erase wit hin the given voltage pulsewidth. The typical erasing time is about 40 0 ms and the final erased threshold voltage is accurately controlled v ia the base level read mode voltage within 0.3 V, The proposed scheme can be used for high throughput erasing in low voltage, high density, multilevel operation split-gate flash memory cells.