DESIGN AUTOMATION OF REED-SOLOMON CODECS USING VHDL

This paper describes the development of a VHDL core for generating Ree d-Solomon codecs. The parameters of the required Reed-Solomon code are entered into the VHDL core as constants (generics) and the resulting description can then be synthesized to any appropriate technology. Cod ecs generated using the core have been shown to be hardware efficient, with design times a fraction of those required for handcrafted design s and the core can therefore be used by any non-specialist to generate Reed-Solomon codecs for any application. (C) 1998 Elsevier Science Lt d. All rights reserved.