CARRIER POCKET ENGINEERING TO DESIGN SUPERIOR THERMOELECTRIC-MATERIALS USING GAAS ALAS SUPERLATTICES/

A large enhancement in the thermoelectric figure of merit for the whol e superlattice, Z(3D)T, is predicted for short-period GaAs/AlAs superl attices relative to bulk GaAs. Various superlattice parameters (superl attice growth direction, superlattice period, and layer thicknesses) a re explored to optimize Z(3D)T, including quantum well states formed f rom carrier pockets at various high symmetry points in the Brillouin z one. The highest room-temperature Z(3D)T obtained in the present calcu lation is 0.41 at the optimum carrier concentration for either (001)- or oriented GaAs (20 Angstrom)/AlAs (20 Angstrom) superlattices, which is about 50 times greater than the corresponding ZT for bulk GaAs. (C ) 1998 American Institute of Physics. [S0003-6951(98)01546-0].