DESIGN AND IMPLEMENTATION OF GANG SCHEDULER ON MULTI-NODE SX-4 AND SX-5 SUPERCOMPUTER SYSTEMS

SX-4 and SX-5 series multi-node models have distributed shared memory architecture with 16 or 32 nodes connected together through an IXS (In ternode Crossbar Switch). Each node is a complete 32 or 16 processor s hared memory parallel vector supercomputer. Parallelization of applica tions, both within a node and across multiple nodes, can take full adv antage of the performance of the series. However, to achieve the highe st possible performance, careful attention to job and processor schedu ling is required so as to ensure that sufficient resources are always available precisely when required. The general requirement is to minim ize waiting time for any system resource such as memory, processor, or storage. Ln the case of processor resource, this is sometimes difficu lt under general multiprocessing conditions with multiple parallelized applications simultaneously contending for processor resource. This p aper presents the design of the Gang scheduler in the SUPER-UX operati ng system as used on all SX series systems. The Gang scheduler automat ically and efficiently synchronizes the allocation of processors even in a multiple parallel job environment where total available processor s are oversubscribed.