ON THE APPLICATION OF SYMBOLIC TECHNIQUES TO THE MULTIPLE-FAULT LOCATION IN LOW TESTABILITY ANALOG CIRCUITS

A new approach for the multiple fault location in linear analog circui ts is proposed. It presents the characteristic of using classical nume rical procedures together with symbolic analysis techniques, which res ult particularly useful in the parametric fault diagnosis field. The p roposed approach is based on the k-fault hypothesis and is provided wi th efficient algorithms for fault location also in the case of low tes tability circuits. The developed algorithms have been used for realizi ng a software package prototype which implements a fully automated sys tem for the fault location in linear analog circuits of moderate size.