A GRAPH REPRESENTATION FOR PROGRAMMABLE LOGIC-ARRAYS TO FACILITATE TESTING AND LOGIC DESIGN

In this paper, we present a new graph model and an associated set of o perations for representing programmable logic arrays (PLA's), The sign al lines and devices of a PLA are represented as the edges and vertice s of a directed graph, respectively, Through this graph model, most re alistic PLA faults, including cross-point, stuck-at, break, and bridgi ng faults, can be modeled and classified, and the maximal diagnosis re solution of a PLA can be determined. Moreover, the model can be easily transformed into a gate-level model, Hence, the work of automatic tes t-pattern generation for a PLA and for other random logic can be done simultaneously. We also show that this representation can be extended to some logic design techniques such as logic minimization, folding, a nd decomposition for PLA's, Thus, this graph model can unify the data structure and operations required in PLA design and test.