K. Chakrabarty et Bt. Murray, DESIGN OF BUILT-IN-TEST GENERATOR CIRCUITS USING WIDTH COMPRESSION, IEEE transactions on computer-aided design of integrated circuits and systems, 17(10), 1998, pp. 1044-1051
We present a method for designing test generator circuits (TGC's) that
incorporate a precomputed test set To in the patterns they produce. O
ur method uses width compression based on the property of d-compatible
s as well as compatibles and inverse compatibles and does not require
access to a gate-level model of the circuit under test. The TGC consis
ts of a counter, which generates a set of encoded test patterns T-E, a
nd a decompression circuit, which consists of simple binary decoders t
hat generate a final sequence containing Tn. We show that partially sp
ecified test sets, i.e., those that contain a large number of don't-ca
res, lead to more efficient TGC's. These TGC's are applicable to embed
ded-core circuits whose detailed designs are not available. We demonst
rate the effectiveness of our approach by presenting experimental resu
lts on; width compression for the ISCAS'85 benchmark circuits and the
full-scan versions of the ISCAS'89 benchmark circuits.