GUARDED EVALUATION - PUSHING POWER MANAGEMENT TO LOGIC SYNTHESIS DESIGN/

The need to reduce the power consumption of, the next generation of di gital systems is clearly recognized at all levels of system design. At the system level, power management is a very powerful technique and d elivers large and unambiguous savings. The ideas behind power manageme nt can be extended to the logic level. This would involve determining which parts of a circuit are computing results that will be used and w hich are not. The parts that are not needed are then ''shut off.'' Thi s paper describes an approach termed guarded evaluation, which is an i mplementation of this idea. A theoretical framework and the algorithms that form the basis of the approach are presented. The underlying ide a is to automatically determine the parts of the circuit that call be disabled on a per-clock-cycle basis. This saves the power used in all the useless transitions in those parts of the circuit. Initial experim ents indicate substantial power savings and the strong potential of th is approach for a large number of benchmark circuits. While this paper presents the development of these ideas at the logic level of design, the same ideas have direct application at the register-transfer Level of design also.