A VERY-LOW POWER-CONSUMPTION, LOW-NOISE ANALOG READOUT CHIP FOR CAPACITIVE DETECTORS WITH A POWER-SUPPLY OF 3.3 V

Authors
HU Y BERST JD SCHAEFFER M
Citation
Y. Hu et al., A VERY-LOW POWER-CONSUMPTION, LOW-NOISE ANALOG READOUT CHIP FOR CAPACITIVE DETECTORS WITH A POWER-SUPPLY OF 3.3 V, Analog integrated circuits and signal processing, 17(3), 1998, pp. 249-260
Citations number
6
Categorie Soggetti
Computer Science Hardware & Architecture","Engineering, Eletrical & Electronic","Computer Science Hardware & Architecture
Journal title
Analog integrated circuits and signal processing → ACNP
ISSN journal
09251030
Volume
17
Issue
3
Year of publication
1998
Pages
249 - 260
Database
ISI
SICI code
0925-1030(1998)17:3<249:AVPLAR>2.0.ZU;2-0
Abstract
An analog frontend block of a VLSI readout chip, dedicated to high spa tial resolution X or beta ray imaging, using capacitive silicon detect ors, is described. In the present prototype, an ENC noise of 343 elect rons at 0 pF with a noise slope of 28 electrons/pF has been obtained f or a peaking time of 10 mu s, a 37 mV/fC conversion gain, a 3.5 V powe r supply and a 150 mu W/channel power consumption.