POSSIBILITIES AND LIMITATIONS OF I-DDQ TESTING IN SUBMICRON CMOS

Citation
J. Figueras et A. Ferre, POSSIBILITIES AND LIMITATIONS OF I-DDQ TESTING IN SUBMICRON CMOS, IEEE transactions on components, packaging, and manufacturing technology. Part B, Advanced packaging, 21(4), 1998, pp. 352-359
Citations number
42
Categorie Soggetti
Engineering, Eletrical & Electronic","Engineering, Manufacturing","Material Science
ISSN journal
10709894
Volume
21
Issue
4
Year of publication
1998
Pages
352 - 359
Database
ISI
SICI code
1070-9894(1998)21:4<352:PALOIT>2.0.ZU;2-G
Abstract
I-DDQ Testing is a well accepted testing approach based on the observa tion of the quiescent current consumption. Its growing industrial impl ementation is based on the possibility of detecting defects which esca pe other more traditional testing methods, However, its application co sts are higher and its effectiveness in deep submicron technologies ma y decrease if the current trend of leakage increase is not stopped by creative innovation.