Y. Nakase et al., COMPLEMENTARY HALF-SWING BUS ARCHITECTURE AND ITS APPLICATION FOR WIDE-BAND SRAM MACROS, IEE proceedings. Circuits, devices and systems, 145(5), 1998, pp. 337-342
A complementary half-swing bus architecture is proposed for high speed
and low power operation. The bus is composed of pairs of lines. The b
us operates with three steps every cycle. In the first two steps, both
bus lines within a pair are set at a half of the supply voltage. In t
he last step, each bus level is determined independently according to
their data whether it is driven to the supply voltage or ground level,
or remains unchanged. Then, each bus line swings the upper or lower h
alf of the supply voltage exclusively. This simple architecture is abl
e to transfer data in mutual direction at higher speed without an area
penalty. It is applied to an SRAM macro with 112-bit bus tor an ATM s
witch LSI. The 84K-bit macro is fabricated in an area of 3.5mm x 4.2mm
with a 0.5 mu m CMOS process technology. Experimental results indicat
e that it operates beyond 200MHz at the supply voltage of 3.3V. From a
cross-talk consideration, the cross-talk works such as to enlarge the
operation margin. Simulation results show that the worst case power d
issipation and the peak current due to simultaneous switching are redu
ced by half and by 66%, respectively, compared with full swing archite
ctures.