TECHNOLOGY SCALING EFFECTS ON MULTIPLIERS

Since integrated circuits were invented, fabrication engineers have be en able to steadily decrease the dimensions of the devices (transistor s). These reductions in the minimum feature sizes have resulted in imp roved performance. In addition. the dimensions of the interconnect use d to connect the active transistors have also scaled. The decreasing d imensions of the physical devices causes the capacitance and resistanc es of the different parts of the multiplier to change. Therefore, the relative delay due to each part of the multiplier changes. In addition , the different encoding schemes used to generate the partial products and the different topologies used in the reduction of the partial pro ducts effect the total latency of the multiplier. This paper examines the effects of the smaller device dimensions on multipliers. It shows that the interconnect is becoming more important and that automatic ge neration of partial products provides the minimum latency for small fe ature sizes.