NEW LOW-COMPLEXITY BIT-PARALLEL FINITE-FIELD MULTIPLIERS USING WEAKLYDUAL BASES

New structures of bit-parallel weakly dual basis (WDB) multipliers ove r the binary ground field are proposed. An upper bound on the size com plexity of bit-parallel multiplier using an arbitrary generating polyn omial is given. When the generating polynomial is an irreducible trino mial x(m) + x(k) + 1, 1 less than or equal to k less than or equal to right perpendicular m/2 left perpendicular, the structure of the propo sed bit-parallel multiplier requires only m(2) two-input AND gates and at most m(2)-1 XOR gates. The time delay is no greater than T-A + (in verted right perpendicular log(2) m inverted left perpendicular + 2) T -X, where T-A and T-X are the time delays of an AND gate and an XOR ga te. respectively.