POWER-AREA TRADE-OFFS IN DIVIDED WORD LINE MEMORY ARRAYS

Since on-chip caches account for a significant portion of the power bu dget of modern microprocessors, low power caches are needed in micropr ocessors destined for portable electronic applications. A significant portion of the power consumption of caches comes from accessing the ca che memory array and most of the power consumption of the memory array comes from driving the bit line pairs (i.e., the column current). Var ious memory array architectures have been proposed to improve the word line delay and the column current. For example, in a divided word lin e memory array, memory cells in each row are organized into blocks. On ly the memory cells which are in the activated block have their bit li ne pairs driven, thus both improving the speed (by decreasing the word line delay) and lowering the power consumption (by decreasing the col umn current). In this paper we analyze the power-area tradeoffs of div ided word line memories with different size blocks. We compare the are a and power consumption of 16 Kbit and 64 Kbit memory arrays with 2, 4 , 8, and 16 memory cells per block. Our experiments show that a divide d word line memory array can lower the power consumption by 50% to 90% over a nondivided word line memory array. However, they consume more area; the area of a divided word line memory array can be 15% to 27% l arger than the areas of a comparable nondivided word line array. Our e xperiments also showed that divided word line memory arrays with two o r four memory cells in a block have better power-area products than th ose with more than four cells per block.