FPGA-BASED PARALLEL ASIP ARCHITECTURE FOR REACTIVE SYSTEMS

Authors
BUCHENRIEDER K KRESS R PYTTEL A SEDLMEIER A VEITH C
Citation
K. Buchenrieder et al., FPGA-BASED PARALLEL ASIP ARCHITECTURE FOR REACTIVE SYSTEMS, Electronics Letters, 33(10), 1997, pp. 842-843
Citations number
5
Categorie Soggetti
Engineering, Eletrical & Electronic
Journal title
Electronics Letters → ACNP
ISSN journal
00135194
Volume
33
Issue
10
Year of publication
1997
Pages
842 - 843
Database
ISI
SICI code
0013-5194(1997)33:10<842:FPAAFR>2.0.ZU;2-H
Abstract
A scalable parallel ASIP architecture based on FPGAs suitable for the implementation of reactive systems is described. The specification lan guage used is extended statecharts. An industrial example requiring th e real-time control of several stepper motors illustrates the benefits of the approach.