A 250 MHZ DUAL-PORT CURSOR RAM USING DYNAMIC DATA ALIGNMENT ARCHITECTURE

Cursor RAMs have been composed of two memory planes. A cursor pattern is stored in these planes with 2-bit data depth. While the pixel port requires data from both planes at the same time, the MPU port accesses either one of the planes at a time. Since the address space is define d differently between the ports, conventional cursor RAMs could not ha ve dealt with these different access ways at real time. This paper pro poses a dual port cursor RAM with a dynamic data alignment architectur e. The architecture processes the different access ways at real time, and reduces a large amount of control circuitry. Conventional cursor R AMs have been organized with a single port memory because dual port me mory cells have been large. We have applied the port swap architecture which has reduced the cell size. The control block is further simplif ied because the controller no longer emulate a dual port memory. The c ursor RAM with these architectures is fabricated with a double metal 0 .5 mu m CMOS process technology. The active area is 1.5 x 1.6 mm(2) in cluding a couple of shift registers and a control block. It operates u p to 263 MHz at the supply voltage of 3.3 V.