A 200-MSPS 6-BIT FLASH ADC IN 0.6-MU-M CMOS

This paper describes a 6-bit Flash analog-to-digital converter (ADC) w hich performs the sampling function in a partial-response, maximum-lik elihood (PRML) disk drive read channel. It operates with sampling freq uencies up to 200 MSPS and achieves an effective number of bits (ENOB) of 5.5 bits with F-in = 50 MHz and 5.0 bits at F-in = 100 MHz. It con sumes 380 mW at 5 V and occupies 2.7 mm(2), Other features include a b it-error rate of <1e-10 and a programmable nonlinear transfer function .