INVESTIGATION OF INTERFACE TRAPS IN LDD PMOSTS BY THE DCIV METHOD

Interface traps in submicron buried-channel LDD pMOST's, generated und er different stress conditions, are investigated by the direct-current current-voltage (DCIV) technique. Two peaks C and D in the DCIV spect rum are found corresponding to interface traps generated in the channe l region and in the LDD region respectively. The new DCIV results clar ify certain issues of the underlying mechanisms involved on hot-carrie r degradation in LDD pMOST's. Under channel hot-carrier stress conditi ons, the hot electron injection and electron trapping in the oxide occ urs for all stressing gate voltage. How ever, the electron injection i nduced interface trap spatial location changes from the LDD region to the channel region when the stressing gate voltage changes from low to high.