HIGH-PERFORMANCE 0.07-MU-M CMOS WITH 9.5-PS GATE DELAY AND 150 GHZ F(T)

Citation
C. Wann et al., HIGH-PERFORMANCE 0.07-MU-M CMOS WITH 9.5-PS GATE DELAY AND 150 GHZ F(T), IEEE electron device letters, 18(12), 1997, pp. 625-627
Citations number
7
ISSN journal
07413106
Volume
18
Issue
12
Year of publication
1997
Pages
625 - 627
Database
ISI
SICI code
0741-3106(1997)18:12<625:H0CW9G>2.0.ZU;2-5
Abstract
We report room-temperature 0.07-mu m CMOS inverter delays of 13.6 ps a t 1.5 V and 9.5 ps at 2.5 V for SOI substrate; 16 ps at 1.5 V and 12 p s at 2.5 V for bulk substrate. This is the first room-temperature sub- 10 ps inverter ring oscillator delay ever reported. PFET with very hig h drive current and reduction in parasitic resistances and capacitance s for both NFET and PFET, realized by careful thermal budget optimizat ion, contribute to the fast device speed. Moreover, the fast inverter delay was achieved without compromising the device short-channel chara cteristics. At V-dd = 1.5 V and I-off similar to 2.5 nA/mu m, minimum L-eff is about 0.085 mu m for NFET and 0.068 mu m for PFET. PFET I-on is 360 mu A/mu m, which is the highest PFET I-on ever reported at comp arable V-dd and I-off. The SOI MOSFET has about one order of magnitude higher I-off than bulk MOSFET due to the floating-body effect. At aro und 0.07 mu m L-eff, the NFET cut-off frequencies are 150 GHz for SOI and 135 GHz for bulk. These performance figures suggest that sub-tenth -micron CMOS is ready for multi-gigahertz digital circuits, and has a good potential for RF and microwave applications.