The S/390(R) Parallel Enterprise Server Generation 4 processor is an i
mplementation of the IBM ESA/390(TM) architecture on a single custom C
MOS chip. It was designed on a blank slate after consideration of rema
pping either a prior CMOS design or a prior bipolar design. It uses a
straightforward pipeline both to achieve a fast cycle time and to spee
d the design cycle. The complex instructions are implemented using hig
hly privileged subroutines called millicode. To achieve high data inte
grity while maintaining a high clock frequency, the chip contains dupl
icate I-and E-units which perform the same operations each cycle and h
ave their results compared.