CIRCUIT-DESIGN TECHNIQUES FOR THE HIGH-PERFORMANCE CMOS IBM S 390 PARALLEL ENTERPRISE SERVER G4 MICROPROCESSOR/

This paper describes the circuit design techniques used for the IBM S/ 390(R) Parallel Enterprise Server G4 microprocessor to achieve operati on up to 400 MHz. A judicious choice of process technology and concurr ent top-down and bottom-up design approaches reduced risk and shortene d the design time. The use of timing-driven synthesis/placement method ologies improved design turnaround time and chip timing. The combined use of static, dynamic, and self-resetting CMOS (SRCMOS) circuits faci litated the balancing of design time and performance return. The use o f robust PLL design, floorplanning, and clock distribution minimized c lock skew. Innovative latch designs permitted performance optimization without adding risk. Microarchitecture optimization and circuit innov ations improved the performance of timing-critical macros. Full custom array design with extensive use of SRCMOS circuit techniques resulted in an on-chip L1 cache having 2.0-ns cycle time.