STANDARD-CELL-BASED DESIGN METHODOLOGY FOR HIGH-PERFORMANCE SUPPORT CHIPS

We describe the methodology used for the design of a set of CMOS suppo rt chips used in the IBM S/390(R) Parallel Enterprise Server Generatio ns 3 and 4, The logic design is based on functional units, and the maj ority of the logic is implemented by standard cell elements placed and routed flat, using timing-driven techniques, Custom library elements are used wherever needed for performance reasons, Using this approach, a density has been achieved that is comparable to those of contempora ry custom designs, combined with very attractive turnaround times.