DESIGN METHODOLOGY FOR THE S 390 PARALLEL ENTERPRISE SERVER G4 MICROPROCESSORS/

Citation
Kl. Shepard et al., DESIGN METHODOLOGY FOR THE S 390 PARALLEL ENTERPRISE SERVER G4 MICROPROCESSORS/, IBM journal of research and development, 41(4-5), 1997, pp. 515-547
Citations number
51
Categorie Soggetti
Computer Sciences","Computer Science Hardware & Architecture
ISSN journal
00188646
Volume
41
Issue
4-5
Year of publication
1997
Pages
515 - 547
Database
ISI
SICI code
0018-8646(1997)41:4-5<515:DMFTS3>2.0.ZU;2-H
Abstract
This paper describes the design methodology employed in the design of the S/390(R) Parallel Enterprise Server G4 microprocessors. Issues of verifying design metrics of area, power, noise, timing, testability, a nd functional correctness are discussed within the context of a transi stor-level custom design approach, Practical issues of managing the co mplexity of a 7.8-million-transistor design and encouraging design pro ductivity are introduced.