FUNCTIONAL VERIFICATION OF THE CMOS S 390 PARALLEL ENTERPRISE SERVER G4 SYSTEM/

Verification of the S/390(R) Parallel Enterprise Server G4 processor a nd level 2 cache, (L2) chips was performed using a different approach than previously, This paper describes the methods employed by our func tional verification team to demonstrate that its logical system compli ed with the S/390 architecture while staying within the changing cost structure and time-to-market constraints, Verification proceeded at fo ur basic levels defined by the breadth of logic being tested, The lowe st level, designer macro verification, contained a single designer's h ardware description language (in VHDL), Unit-level verification consis ted of a logical portion of function that generally contained four or five designers' logic, The third level of verification was the chip le vel, in which the processor or L2 chips were individually tested, Fina lly, system-level verification was performed on symmetric multiprocess or (SMP) configurations that included bus-switching network (BSN) chip s and I/O connection chips, designated as memory bus adaptors (MBAs), along with multiple copies of the processor and L2 chips.