FORMAL VERIFICATION MADE EASY

Formal verification (FV) is considered by many to be complicated and t o require considerable mathematical knowledge for successful applicati on. We have developed a methodology in which we have added formal veri fication to the verification process without requiring any knowledge o f formal verification languages, We use only finite-state machine nota tion, which is familiar and intuitive to designers. Another problem as sociated with formal verification is state-space explosion. If that oc curs, no result is returned; our method switches to random simulation after one hour without results, and no effort is lost. We have compare d FV against random simulation with respect to development time, and o ur results indicate that FV is at least as fast as random simulation, FV is superior in terms of verification quality, however, because it i s exhaustive.