DESIGNER-LEVEL VERIFICATION USING TIMEDIAG GENRAND/

TIMEDIAG/GENRAND is a tool set used on various portions of the CMOS pr ocessor for the IBM S/390(R) Parallel Enterprise Server Generation 4 t o assist in designer-level logic verification, The concept of surround ing the logic design (hereafter referred to simply as ''logic'') under test with irritator behaviorals, a methodology developed and proven e ffective on larger simulation models, is moved to the designer level w ithout the overhead of writing multiple behaviorals. Rather than writi ng source-level (e.g., VHDL, C code, etc.) behaviorals, the method cre ates an external stimulus to the design by using a series of generaliz ed timing diagrams that obey the interface protocols of the logic unde r test, These timing diagrams are entered using the TIMEDIAG (timing d iagram) editor, The effort required for logic verification is thus lim ited to understanding and laying out the interfaces to the design-a ta sk that must be done for any well-designed unit of logic, regardless o f whether or not it is being verified at the designer level, Once the timing diagrams are written, GENRAND (general random driver) is invoke d to run simulation on the design, GENRAND randomly initiates the timi ng diagrams that obey the interface protocol, causing many different i nput and output permutations, This simulation is very effective in tes ting the logic implementation.