In a recent paper, Spina and Upadhyaya presented a method for the fault dia
gnosis of analog linear circuits. The method, which is based on a white noi
se generator and an artificial neural network for response analysis, has be
en applied to circuits of reasonable dimensions, taking into account the ef
fect of the component tolerances. However, the proposed method does not tak
e into account the testability analysis of the circuit under test. Research
on testability analysis of linear circuits has been developed by several a
uthors in the last 20 years, and algorithms and programs for testability ev
aluation have been presented in several publications. It is our opinion tha
t the testability analysis concept could be useful in the approach proposed
by Spina and Upadhyaya to improve the quality of the results even further.
In this brief, me discuss this possibility.