Board-level partitioning for partial scan using fuzzy logic

We present a board-level partitioning scheme for improved partial scan on t he resulting integrated circuits (IC's). Fuzzy logic rules and two adaption techniques allow us to simultaneously minimize four important independent objective functions in the examined problem formulation. The maximum among all sets in the partitionare the following quantities: 1) number of scanned nodes in a set; 2) number of incident nets to a set; 3) number of inputs t o any set; and finally 4) the period of the global clock. The sets must sat isfy upper and lower capacity bounds. We experimented with some ISCAS'89 be nchmark circuits and we compared the performance of our tool with four iter ative improvement heuristics, each considering only one of the four differe nt functions. Our experimental results indicate that the performance of the proposed tool is very effective.