Board-level partitioning for partial scan using fuzzy logic

Citation
S. Tragoudas et al., Board-level partitioning for partial scan using fuzzy logic, IEEE FUZ SY, 7(2), 1999, pp. 241-249
Citations number
19
Categorie Soggetti
AI Robotics and Automatic Control
Journal title
IEEE TRANSACTIONS ON FUZZY SYSTEMS
ISSN journal
10636706 → ACNP
Volume
7
Issue
2
Year of publication
1999
Pages
241 - 249
Database
ISI
SICI code
1063-6706(199904)7:2<241:BPFPSU>2.0.ZU;2-Z
Abstract
We present a board-level partitioning scheme for improved partial scan on t he resulting integrated circuits (IC's). Fuzzy logic rules and two adaption techniques allow us to simultaneously minimize four important independent objective functions in the examined problem formulation. The maximum among all sets in the partitionare the following quantities: 1) number of scanned nodes in a set; 2) number of incident nets to a set; 3) number of inputs t o any set; and finally 4) the period of the global clock. The sets must sat isfy upper and lower capacity bounds. We experimented with some ISCAS'89 be nchmark circuits and we compared the performance of our tool with four iter ative improvement heuristics, each considering only one of the four differe nt functions. Our experimental results indicate that the performance of the proposed tool is very effective.