Passivation of InP-based heterostructure bipolar transistors in relation to surface Fermi level

The effect of surface Fermi level position on dc-characteristics of InP- ba sed heterostructure bipolar transistors (HBT) is reported. The Fermi level of an InP surface covered with silicon oxide was located at an energy posit ion close to the conduction band minimum of InP. This implies that an elect ron accumulation layer forms at the interface, which acts as a surface leak age path. The HBT passivated with silicon oxide films showed large excess b ase current and poor current gain. In contrast, the Fermi level position at the silicon nitride/InP interface was found to be near the midgap, and no electron accumulation layer was formed at the interface. The HBT passivated with silicon nitride film showed excellent de characteristics with very sm all, excess base current.