High speed self-timed pipelined datapath for square rooting

Citation
G. Cappuccino et al., High speed self-timed pipelined datapath for square rooting, IEE P-CIRC, 146(1), 1999, pp. 16-22
Citations number
11
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS
ISSN journal
13502409 → ACNP
Volume
146
Issue
1
Year of publication
1999
Pages
16 - 22
Database
ISI
SICI code
1350-2409(199902)146:1<16:HSSPDF>2.0.ZU;2-S
Abstract
The authors describe a new highperformance self-timed circuit for asynchron ous square rooting. The new architecture is based on a modified nonrestorin g algorithm. An asynchronous pipelined cellular array without auxiliary sys tem for the identification of exceptions will be demonstrated. The self-tim ing approach allows the whole performance to be greatly improved with respe ct to synchronous implementation, causing acceptable area overheads.