Systolic neural algorithms

This paper describes the three neural network training algorithms that have been implemented in the systolic array processor [1]. It describes the ind ividual stages of each algorithm, along with any requirements for constant data values within the array, as well as details for any instructions that are 'locked' into a PE for perpetual execution. Dataflow diagrams within th e systolic array for each stage of each algorithm, showing the implications of each calculation and the implied direction of the execution flow, are a lso shown and timing information for each stage of each algorithm are also given.