Strategy for power efficient combined task and data parallelism exploration illustrated on a QSDPCM video codec

Application studies indicate that between 50% and 80% of the power cost in image and video processing systems is due to data storage and transfers. Th is is especially true for multi-processor realizations, because conventiona l parallelization strategies ignore this cost and focus only on the perform ance, whereas the power consumption also depends heavily on the way a syste m is parallelized. We will demonstrate the impact of processor partitioning on the memory requirements by exploring a QSDPCM video codec realization. Furthermore, we show that a strategy for combined task and data parallelism exploration leads to a significant power reduction. (C) 1999 Elsevier Scie nce B.V. All rights reserved.