The effect of emitter overetch and base implantation tilt on the performance of double polysilicon bipolar transistors

In a self-aligned double polysilicon bipolar junction transistor (BJT) proc ess, the emitter window is opened by etching through the base polysilicon. The etch always penetrates a certain depth (overetch depth) into the upper epitaxial layer of the silicon substrate. Experimental results, confirmed b y process and device simulation show that the cut-off frequency f(T), incre ases with overetch depth. According to the simulation, the increase in f(T) is a consequence of a shorter base width along the perimeter of the intrin sic base. The base shortening results from the weakened electrical link bet ween the extrinsic and intrinsic base which in turn is caused by the emitte r window overetch. It is found that the f(T), dependence upon overetch dept h is stronger for 7 degrees than for 0 degrees wafer tilt during the intrin sic base ion implantation During the implantation with a 7 degrees tilt, th e emitter window sidewalls lead to the formation of an even shorter base wi dth along part of the perimeter of the intrinsic base. However, excessive e mitter window overetch degrades the BJT performance in general, resulting i n high collector leakage current, low emitter-to-collector breakdown voltag e and low maximum oscillation frequency (f(MAX)). The simulation results al so demonstrate that the effect of emitter overetch and base implantation ti lt will be more severe when the BJT is scaled down to deep-submicron dimens ions.