We have used an inductively coupled plasma (ICP) reactor to etch deep featu
res with SF6/C4F8 pulsed processes. Microelectromechanical system (MEMS) ap
plications require 10-500 mu m deep structures to be etched into silicon. T
he etch rate has to be carefully defined: in plasma etching the etch rate i
s a function of feature size (RIE lag), of etch time (ARDE,aspect ratio dep
endent etching) and loading (pattern density). Three processes have been ch
aracterized with respect to etch rate, loading, RIP-lag, ARDE and sidewall
profile. The high rate process has 5 mu m/min maximum etch rate but it exhi
bits severe RIE-lag and ARDE. Two other processes with maximum etch rates o
f 3.5 mu m/min and 1.6 mu m/min are much less prone to RIE-lag and ARDE. Et
ch profiles and their non-idealities have been studied. Vertical, positivel
y sloped, negatively sloped and barrel-like profiles result depending on pr
ocess and feature size.