Reconfigurable shift switching parallel comparators

We present novel asynchronous VLSI comparator schemes which are based on re cently proposed reconfigurable shift switch logic and the traditional (prec harged) CMOS domino logic. The schemes always produce a semaphore as a by-p roduct of the process to indicate the end of domino process, which requires no additional delay and a minimal number of additional devices. For a larg e percentage of inputs the computations are much faster than traditional sy nchronous comparators due to the full utilization of the inherent speed of the circuits. Also the schemes are simple, area compact and stable.