Enhanced code compression for embedded RISC processors

This paper explores compiler techniques for reducing the memory needed to l oad and run program executables. In embedded systems, where economic incent ives to reduce both RAM and ROM are strong, the size of compiled code is in creasingly important. Similarly, in mobile and network computing, the need to transmit an executable before running it places a premium on code size. Our work focuses on reducing the size of a program's code segment, using pa ttern-matching techniques to identify and coalesce together repeated instru ction sequences. In contrast to other methods, our framework preserves the ability to run program executables directly, without an intervening decompr ession stage. Our compression framework is integrated into an industrial-st rength optimizing compiler, which allows us to explore the interaction betw een code compression and classical code optimization techniques, and requir es that we contend with the difficulties of compressing previously optimize d code. The specific contributions in this paper include a comprehensive ex perimental evaluation of code compression for a RISC-like architecture, a m ore powerful pattern-matching scheme for improved identification of repeate d code fragments, and a new form of profile-driven code compression that re duces the speed penalty arising from compression.