A new approach for computing higher-order moments on linear systolic arrays

The last few years have witnessed significant advances in the use of higher -order moments in various signal processing applications. As a result, the demand for efficient architectural designs for these functions is on the ri se. In this paper we present a new formulation for implementing third- and fourth-order moments on linear systolic arrays. In the proposed approach th e moments are computed as elements of a matrix which are obtained after a s eries of matrix multiplication operations. The resultant architecture is a simple linear array that can be implemented efficiently in VLSI.