Fast hopping frequency synthesizer using difference of phase errors

Citation
T. Oie et al., Fast hopping frequency synthesizer using difference of phase errors, ELEC C JP 1, 82(10), 1999, pp. 10-19
Citations number
8
Categorie Soggetti
Information Tecnology & Communication Systems
Journal title
ELECTRONICS AND COMMUNICATIONS IN JAPAN PART I-COMMUNICATIONS
ISSN journal
87566621 → ACNP
Volume
82
Issue
10
Year of publication
1999
Pages
10 - 19
Database
ISI
SICI code
8756-6621(199910)82:10<10:FHFSUD>2.0.ZU;2-L
Abstract
Fast frequency hopped-spread spectrum (FFH-SS) communication is a system th at can realize excellent interference immunity, disturbance immunity, and s ecurity. In the implementation of this system, there must be a synthesizer that can switch the frequency with high speed. From such a viewpoint, the a uthors previously proposed a fast hopping PLL synthesizer, based on the ini tial value presentation in which the phase difference obtained by the phase comparator at the same frequency output of the previous period is reproduc ed by utilizing the periodicity of the frequency hopping. It is shown that the hopping frequency can be raised to one-third the reference frequency. I n this method, however, the phase error of the VCO output generated in freq uency switching produces an error in the phase difference reproduced by the phase comparator, which results in a stepwise error in the output frequenc y. In order to deal with this problem, a circuit for the phase error compen sation was proposed, but there remained problems such as the difficulty of high-frequency operation. This paper proposes a fast hopping frequency synt hesizer that solves those problems. In the proposed method, the phase diffe rence is not reproduced by the phase comparator, and there is no effect fro m phase error of the VCO output generated infrequency switching due to the use of the difference of the phase errors. Faster operation is realized, wi th the hopping frequency equal to one-half the reference frequency. This he lps to reduce the number of bits in the A/D converter below that of the D/A converter. (C) 1999 Scripta Technica, Electron Comm Jpn Pt 1, 82(10): 10-1 9, 1999.