A portable digital DLL for high-speed CMOS interface circuits

Citation
Bw. Garlepp et al., A portable digital DLL for high-speed CMOS interface circuits, IEEE J SOLI, 34(5), 1999, pp. 632-644
Citations number
16
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE JOURNAL OF SOLID-STATE CIRCUITS
ISSN journal
00189200 → ACNP
Volume
34
Issue
5
Year of publication
1999
Pages
632 - 644
Database
ISI
SICI code
0018-9200(199905)34:5<632:APDDFH>2.0.ZU;2-R
Abstract
A digital delay-locked loop (DLL) that achieves infinite phase range and 40 -ps worst case phase resolution at 400 MHz was developed in a 3.3-V, OA-mu m standard CMOS process. The DLL uses dual delay lines with an end-of-cycle detector, phase blenders, and duty-cycle correcting multiplexers, This mor e easily process-portable DLL achieves jitter performance comparable to a m ore complex analog DLL when placed into identical high-speed interface circ uits fabricated on the same test-chip die. At 400 MHz, the digital DLL prov ides <250 ps peak-to-peak long-term jitter at 3.3 V and operates down to 1. 7 V, where it dissipates 60 mW, The DLL occupies 0.96 mm(2).