A digital delay-locked loop (DLL) that achieves infinite phase range and 40
-ps worst case phase resolution at 400 MHz was developed in a 3.3-V, OA-mu
m standard CMOS process. The DLL uses dual delay lines with an end-of-cycle
detector, phase blenders, and duty-cycle correcting multiplexers, This mor
e easily process-portable DLL achieves jitter performance comparable to a m
ore complex analog DLL when placed into identical high-speed interface circ
uits fabricated on the same test-chip die. At 400 MHz, the digital DLL prov
ides <250 ps peak-to-peak long-term jitter at 3.3 V and operates down to 1.
7 V, where it dissipates 60 mW, The DLL occupies 0.96 mm(2).