A 2.5-V, 72-Mbit, 2.0-GByte/s packet-based DRAM with a 1.0-Gbps/pin interface

A 2.5-V, 72-Mbit DRAM based on packet protocol has been developed using 1) a rotated hierarchical I/O architecture to reduce power noise and to minimi ze the chip-size penalty associated with an 8-bit prefetch architecture imp lemented with 16 internal banks and 144 I/O lines, 2) a delay-locked-loop c ircuit using a high-speed and small-swing differential clock to achieve the peak bandwidth of 2.0 GByte/s in a single chip with low noise sensitivity, and 3) a flexible column redundancy scheme to efficiently increase redunda ncy coverage using a shifted I/O line scheme for multibank architecture.