A 5-GByte/s data-transfer scheme with bit-to-bit skew control for synchronous DRAM

This paper describes a 5-GByte/s data-transfer scheme suitable for synchron ous DRAM memory systems. To achieve a higher data-transfer frequency, the e lectrical properties were improved based on the frequency analysis of the m emory system. Then, a bit-to-bit skew compensation technique that eliminate s incongruent skew between the signals is described with a new, multioutput controlled delay circuit to accomplish bit-to-bit skew compensation by con trolling transmission timing of every data bit. Simulated maximum data-tran sfer rate of the proposed memory system resulted in 5.1/5.8 GByte/s (321/36 5 MHz, x64 bit, double data rate) for data write/read operation, respective ly.