A negative V-th cell architecture for highly scalable, excellently noise-immune, and highly reliable NAND flash memories

A new, negative V-th cell architecture is proposed where both the erased an d the programmed state have negative Vth This architecture realizes highly scalable, excellently noise-immune, and highly reliable NAND flash memories , The program disturbance that limits the scaling of a local oxidation of s ilicon (LOCOS) width in a conventional NAND-type cell is drastically reduce d. As a result, the scaling limit of the LOGOS width decreases from 0.56 to 0.45 mu m, which leads to 20% isolation width reduction, The proposed cell is essential for the future scaled shallow trench isolated cells because i mproved program disturb characteristics can be obtained irrespective of the process technology or feature size. New circuit techniques, such as a PMOS drive column latch and a V-cc-bit-line shield sensing method are also util ized to realize the proposed cell operation. By using these novel circuit t echnologies, array noise, such as a source-line noise [1] and an inter-bit- line capacitive coupling noise [2], are eliminated, Consequently, the Vth f luctuation due to array noise is reduced from 0.7 to 0.1 V, and the V-th di stribution width decreases from 1.2 to 0.6 V, In addition to the smaller ce ll size and the high noise immunity, the proposed cell improves device reli ability. The read disturb time increases by more than three orders of magni tude, and a highly reliable operation can be realized.